1 standard products ut54acs164/UT54ACTS164 8-bit shift registers datasheet november 2010 www.aeroflex.com/logic features ? and-gated (enable/ disable) serial inputs ? fully buffered clock and serial inputs ? direct clear ? 1.2 cmos - latchup immune ? high speed ? low power consumption ? single 5 volt supply ? available qml q or v processes ? flexible package - 14-pin dip - 14-lead flatpack ? ut54acs164 - smd 5962-96556 ? UT54ACTS164 - smd 5962-96557 description the ut54acs164 and the UT54ACTS164 are 8-bit shift reg- isters which feature and-gated serial inputs and an asynchro- nous clear. the gated serial inputs (a and b) permit complete control over incoming data. a low at either input inhibits entry of new data and resets the first flip-flop to the low level at the next clock pulse. a high-level at both serial inputs sets the first flip-flop to the high level at the next clock pulse. data at the serial inputs may be changed while the clock is high or low, providing the minimum setup time requirements are met. clock- ing occurs on the low-to-high-level transition of the clock input. the devices are characterized over full military temperature range of -55 c to +125 c. function table notes: 1. q a0 , q b0 , q h0 = the level of q a , q b or q h , respectively, before the indicated steady-state input conditions were established. 2. q an and q gn = the level of q a or q g before the most recent transition of the clock; indicates a one-bit shift. pinouts 14-pin dip top view 14-lead flatpack top view logic symbol inputs outputs clr clk a b q a q b ... q h l x x x l l l h l x x q a0 q b0 q h0 h h h h q an q gn h l x l q an q gn h x l l q an q gn 1 2 3 4 5 7 6 14 13 12 11 10 8 9 a b q a q b q c q d v ss v dd q h q g q f q e clr clk 1 2 3 4 5 7 6 14 13 12 11 10 8 9 v dd q h q g q f q e clr clk a b q a q b q c q d v ss (9) clr (8) clk r 1d note: 1. logic symbol in accordance with ansi/ieee std 91-1984 and iec publication 617-12. (1) a (2) b (3) q a srg8 & (4) q b (5) q c (6) q d (10) q e (11) q f (12) q g (13) q h c1/
2 logic diagram q a (8) clk k k r s k r s k r s k r s k r s k r s k r s q b q c q d q e q f q g q h clr (9) (2) (1) a b serial r s c c c c c c c c (3) (4) (5) (6) (10) (11) (12) (13)
3 operational environment 1 notes: 1. logic will not latchup during radiation ex posure within the limits defined in the table. 2. device storage elements are immune to seu affects. absolute maximum ratings note: 1. stresses outside the listed absolute maxi mum ratings may cause permanent damage to the device. this is a stress rating only, functional operation of the device at these or any other conditions beyond limits indicated in the opera tional sections is not recommend ed. exposure to absolute maxi mum rating conditio ns for extended periods may affect device reliability. recommended operating conditions parameter limit units total dose 1.0e6 rads(si) seu threshold 2 80 mev-cm 2 /mg sel threshold 120 mev-cm 2 /mg neutron fluence 1.0e14 n/cm 2 symbol parameter limit units v dd supply voltage -0.3 to 7.0 v v i/o voltage any pin -.3 to v dd +.3 v t stg storage temperature range -65 to +150 c t j maximum junction temperature +175 c t ls lead temperature (soldering 5 seconds) +300 c jc thermal resistance junction to case 20 c/w i i dc input current 10 ma p d maximum power dissipation 1 w symbol parameter limit units v dd supply voltage 4.5 to 5.5 v v in input voltage any pin 0 to v dd v t c temperature range -55 to + 125 c
4 dc electrical characteristics 7 (v dd = 5.0v 10%; v ss = 0v 6 , -55 c < t c < +125 c); unless otherwise noted, tc is per the temperature range ordered. symbol parameter condition min max unit v il low-level input voltage 1 acts acs 0.8 .3v dd v v ih high-level input voltage 1 acts acs .5v dd .7v dd v i in input leakage current acts/acs v in = v dd or v ss -1 1 a v ol low-level output voltage 3 acts acs i ol = 8.0ma i ol = 100 a 0.40 0.25 v v oh high-level output voltage 3 acts acs i oh = -8.0ma i oh = -100 a .7v dd v dd - 0.25 v i os short-circuit output current 2 ,4 acts/acs v o = v dd and v ss -200 200 ma i ol output current 10 (sink) v in = v dd or v ss v ol = 0.4v 8 ma i oh output current 10 (source) v in = v dd or v ss v oh = v dd - 0.4v -8 ma p total power dissipation 2, 8, 9 c l = 50pf 1.9 mw/ mhz i ddq quiescent supply current v dd = 5.5v 10 a i ddq quiescent supply current delta acts for input under test v in = v dd - 2.1v for all other inputs v in = v dd or v ss v dd = 5.5v 1.6 ma c in input capacitance 5 ? = 1mhz @ 0v 15 pf c out output capacitance 5 ? = 1mhz @ 0v 15 pf
5 notes: 1. functional tests are conducted in accordance with mil-std-883 with the followi ng input test conditions: v ih = v ih (min) + 20%, - 0%; v il = v il (max) + 0%, - 50%, as specified herein, for ttl, cmos, or schmitt compatible inputs. devices may be tested using any inpu t voltage within the above specified range, but are guaranteed to v ih (min) and v il (max). 2. supplied as a design limit bu t not guaranteed or tested. 3. per mil-prf-38535, for current density 5.0e5 amps/cm 2 , the maximum product of load capac itance (per output buff er) times frequency should not exceed 3,765 pf/mhz. 4. not more than one output may be shorted at a time for maximum duration of one second. 5. capacitance measured for initial qualifi cation and when design changes may affect the value. capacitance is measured between the designated terminal and v ss at frequency of 1mhz and a signal amplitude of 50mv rms maximum. 6. maximum allowable relative shift equals 50mv. 7. all specifications valid for radiation dose 1e6 rads(si). 8. power does not include power contribution of any ttl output sink current 9. power dissipation specified per switching output. 10. this value is guaranteed based on characterization data, but not tested.
6 ac electrical characteristics 2 (v dd = 5.0v 10%; v ss = 0v 1 , -55 c < t c < +125 c); unless otherwise noted, tc is per the temperature range ordered. notes: 1. maximum allowable relative shift equals 50mv. 2. all specifications valid for radiation dose 1e6 rads(si). 3. based on characterization, hold time (t h ) of 0ns can be assumed if data setup time (t su2 ) is > 10ns. this is guaran teed, but not tested. symbol parameter minimum maximum unit t phl clk to qn 4 21 ns t plh clk to qn 2 18 ns t phl clr to qn 5 21 ns f max maximum clock frequency 83 mhz t su1 clr inactive setup time before clk 4 ns t su2 data setup time before clk 4 ns t h 3 data hold time after clk 2 ns t w minimum pulse width clr low clk high clk low 6 ns
7 packaging side-brazed packages
8 flatpack packages
9 ut54acs164/UT54ACTS164: smd 5962 ***** ** * * * * lead finish: (notes 1 & 2) a = solder c = gold x = optional package type: x = 14-lead ceramic botto m-brazed dual-in-line flatpack c = 14-lead ceramic side-brazed dip class designator: q = qml class q v = qml class v device type: 01 drawing number : 96556 = ut54acs164 96557 = UT54ACTS164 total dose: (notes 3 & 4) r = 1e5 rads(si) f = 3e5 rads(si) g = 5e5 rads(si) h = 1e6 rads(si) notes: 1. lead finish (a,c, or x) must be specified. 2. if an ?x? is specified when ordering, pa rt marking will match the lead finish and w ill be either ?a? (solder) or ?c? (gold). 3. total dose radiation must be specified when ordering. qml q and qml v not available without radiation hardening. for protot ype inquiries, contact factory. 4. device type 02 is only offered with a tid tolerance guarantee of 3e5 rads(si) or 1e6 rads(si) and is tested in accordance wi th mil-std-883 test method 1019 condition a and section 3.11.2 . device type 03 is only offered with a tid tolerance guarantee of 1e5 rads(si), 3e5 rads(si) , and 5e5 rads(si), and is tested in accordance with mil-std-883 test method 1019 condition a.
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